Specification Update

Intel
®
Xeon
®
Processor 7000 Series 41
Specification Update, March 2010
A87. VMEntry from 64-bit Host to 32-bit Guest may Cause IERR# with
Hyper-Threading Enabled
Problem: When transitioning from a 64-bit host environment to a 32-bit guest environment via a
VMEntry, internal conditions in a processor with Hyper-Threading enabled may cause a
page-table walk to be prematurely terminated, resulting in a processor hang and the
assertion of IERR#.
Implication: An IERR# may occur on VMEntry from a 64-bit to a 32-bit environment with Hyper-
Threading enabled.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
A88. A Page Fault May Not be Generated When the PS bit is set to “1” in a
PML4E or PDPTE
Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due
to this erratum, PS of such an entry is ignored and no page fault will occur due to its
being set.
Implication: Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
“1”.
Status: For the steppings affected, see the Summary Table of Changes.
A89. FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an 80-
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the
value contained in the FP Data Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.
Intel has not observed this erratum with any commercially available software.
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code
accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses
are wrapped around a 4-Gbyte boundary.
Status: For the steppings affected, see the Summary Table of Changes.