Specification Update

40 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
A83. Processor may hang during entry into No-Fill Mode or No-Eviction
Mode
Problem: Only one logical processor per core can be active when processor is put in No-Fill Mode
or No-Eviction Mode. If the other logical processor is active or there is an internal or
external event pending to wake that logical processor, the processor may hang when
writing to MSR IA32_BIOS_CACHE_AS_RAM (80H).
Implication: A processor may hang due to this erratum. Intel has not observed this erratum with
any commercially available software or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A84. FPU operand pointer may not be cleared following FINIT/FNINIT
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87
FPU Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector
(both fields form the FPUDataPointer). Saving the floating point environment with
FSTENV, FNSTENV, or floating point state with FSAVE, FNSAVE or FXSAVE before an
intervening FP instruction may save uninitialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point
image or floating point environment structure may appear to be random values.
Executing any non-control FP instruction with memory operand will initialize the
FPUDataPointer. Intel has not observed this erratum with any commercially available
software.
Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or floating
point environment saved memory image to be correct, until at least one non-control FP
instruction with a memory operand has been executed.
Status: For the steppings affected, see the Summary Table of Changes.
A85. The IA32_MC0_STATUS/ IA32_MC1_STATUS Overflow Bit is not set
when Multiple Un-correctable Machine Check Errors Occur at the Same
Time
Problem: When two MC0/MC1 enabled un-correctable machine check errors are detected in the
same internal clock cycle, the highest priority error will be logged in
IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set.
Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit in
the IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A86. Debug Status Register (DR6) Breakpoint Condition Detected Flags
May be Set Incorrectly
Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint
condition under certain boundary conditions when either:
• A "MOV SS" or "POP SS" instruction is immediately followed by a hardware
debugger breakpoint instruction, or
• Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a
general-detect exception condition.
Implication: Due to this erratum the breakpoint condition detected flags may be set incorrectly.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.