Specification Update

14 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
A11 X No Fix FSW may not be completely restored after page fault on FRSTOR or FLDENV
instructions
A12 X No Fix Processor issues inconsistent transaction size attributes for locked operation
A13 X No Fix When the processor is in the system management mode (SMM), Debug registers
may be fully writeable
A14 X No Fix Shutdown and IERR# may result due to a machine check exception on a Hyper-
Threading Technology enabled processor
A15 X No Fix Processor may hang under certain frequencies and 12.5% STPCLK# duty cycle
A16 X No Fix System may hang if a fatal cache error causes bus write line (BWL) transaction to
occur to the same cache line address as an outstanding bus read line (BRL) or bus
read-invalidate line (BRIL)
A17 X No Fix VMCALL to activate dual-monitor treatment of SMIS and SMM ignores reserved bit
settings in VM-exit control field
A18 X No Fix Parity error in the L1 cache may cause the processor to hang
A19 X No Fix Locks and SMC detection may cause the processor to temporarily hang
A20 X No Fix Incorrect debug exception (#DB) may occur when a data breakpoint is set on an FP
instruction
A21 X No Fix xAPIC may not report some illegal vector error
A22 X No Fix Incorrect duty cycle is chosen when on-demand clock modulation is enabled in a
processor supporting Hyper-Threading Technology
A23 X No Fix Memory aliasing of pages as uncacheable memory type and write back (WB) may
hang the system
A24 X No Fix Interactions between the instruction translation lookaside buffer (ITLB) and the
instruction streaming buffer may cause unpredictable software behavior
A25 X No Fix Using STPCLK# and executing code from very slow memory could lead to a
system hang
A26 X No Fix Processor provides a 4-byte store unlock after an 8-Byte load lock
A27 X No Fix Data breakpoints on the high half of a floating point line split may not be captured
A28 X No Fix Machine Check exceptions may not update last-exception record MSRs (LERs)
A29 X No Fix MOV CR3 performs incorrect reserved bit checking when in PAE paging
A30 X No Fix Stores to page tables may not be visible to pagewalks for subsequent loads without
serializing or invalidating the page table entry
A31 X No Fix Processor may fault when the upper 8 bytes of segment selector is loaded from a
far jump through a call gate via the local descriptor table
A32 X No Fix Loading a stack segment with a selector that references a non-canonical address
can lead to a #SS fault on a processor supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
A33 X No Fix FXRSTOR may not restore non-canonical effective addresses on processors with
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) Enabled
A34 X No Fix A push of esp that faults may zero the upper 32 bits of RSP
A35 X No Fix Enhanced halt state (C1E) may not be entered in a Hyper-Threading Technology
enabled processor
A36 X No Fix Checking of page table base address may not match the address bit width
supported by the platform
Table 2. Errata (Sheet 2 of 5)
Number A-0 Status Description