Datasheet

Signal Definitions
64 Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
SM_EP_A[2:0] I The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in conjunction with the
upper address bits in order to maintain unique addresses on the SMBus in a system with multiple
processors. To set an SM_EP_A line high, a pull-up resistor should be used that is no larger than
1kΩ
. The processor includes a 10 kΩ pull-down resistor to V
SS
for each of these signals.
For more information on the usage of these pins, see Section 7.4.8.
SM_TS_A[1:0] I The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus in conjunction with
the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple
processors.
The device’s addressing, as implemented, includes a Hi-Z state for both address pins. The use of the
Hi-Z state is achieved by leaving the input floating (unconnected).
For more information on the usage of these pins, see Section 7.4.8.
SM_VCC I SM_VCC provides power to the SMBus components on the Dual-Core Intel Xeon processor 7000
series package.
SM_WP I WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch EEPROM is
write-protected when this input is pulled high to SM_VCC. The processor includes a 10 kΩ pull-down
resistor to V
SS
for this signal.
SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a
System Management Interrupt, processors save the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET#, the processor will tri-state its outputs.
STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-Grant state.
The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units. The processor continues to snoop
bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK#
has no effect on the bus clock; STPCLK# is an asynchronous input.
TCK I TCK (Test Clock) provides the clock input for the processor Test Access Port.
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed
for JTAG specification support.
TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output
needed for JTAG specification support.
TEST_BUS I Must be connected to all other processor TEST_BUS signals in the system. See the appropriate
platform design guideline for termination details.
TESTHI[6:0] I TESTHI[6:0] must be connected to a V
TT
power source through a resistor for proper processor
operation. See Section 2.3 for more details.
THERMTRIP# O The processor protects itself from catastrophic overheating by use of an internal thermal sensor. To
ensure that there are no false trips, THERMTRIP# (Thermal Trip) will activate at a temperature that
is about 20°C above the maximum case temperature (T
C
). Once activated, the processor will stop all
execution and the signal remains latched until RESET# goes active. There is no hysteresis built into
the thermal sensor itself; as long as the die temperature drops below the trip level, a RESET# pulse
will reset the processor and execution will continue. If the temperature has not dropped below the trip
level, the processor will continue to drive THERMTRIP# and remain stopped.
TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRDY# I TRDY# (Target Ready) is asserted by the target (chipset) to indicate that it is ready to receive a write
or implicit writeback data transfer. TRDY# must connect the appropriate pins of all FSB agents.
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven electrically low
during power on Reset. Please refer to the eXtended Debug Port: Debug Port Design Guide for Twin
Castle Chipset Platforms or the eXtended Debug Port: Debug Port Design Guide for MP Platforms
for details.
V
CC
IV
CC
provides power to the core logic of the Dual-Core Intel Xeon processor 7000 series.
Table 5-1. Signal Definitions (Sheet 6 of 7)
Name Type Description