Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 65
Datasheet Volume One, February 2014
Signal Descriptions
5.8 Serial VID Interface (SVID) Signals
5.9 PIROM Signals
TDI TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
TMS TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TRST_N TRST_N (Test Reset) resets the Test Access Port (TAP) logic.
TRST_N must be driven low during power on Reset.
Table 5-8. SVID Signals
SVIDALERT_N Serial VID alert.
SVIDCLK Serial VID clock.
SVIDDATA Serial VID data out.
SVID_IDLE_N Output pin used to indicate when the SVID bus is IDLE. When
asserted true (low), it will assert for two SVID clock cycles. It
guarantees that the SVID bus will remain idle for two SVID clocks
after it deasserts.
Table 5-9. PIROM Signals
PIROM_ADDR[2:0] Address for PIROM (Processor Information ROM/OEM scratchpad).
SM_WP WP (Write Protect) can be used to write protect the Scratch
EEPROM. The Scratch EEPROM is write-protected when this input is
pulled high to VCCSTBY33.
SMBCLK The SMBus Clock (SMBCLK) signal is an input clock which is
required for operation of PIROM. This clock is driven by the SMBus
controller and is asynchronous to other clocks in the processor.
SMBDAT The SMBus Data (SMBDAT) signal is the data signal for the SMBus.
This signal provides the single-bit mechanism for transferring data
between SMBus devices.
Table 5-7. JTAG and TAP Signals (Sheet 2 of 2)
Signal Name Description