Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 61
Datasheet Volume One, February 2014
Thermal Management Specifications
With a properly designed and characterized thermal solution, it is anticipated that
PROCHOT_N will be asserted for very short periods of time when running the most
power intensive applications. An under-designed thermal solution that is not able to
prevent excessive assertion of PROCHOT_N in the anticipated ambient environment
may cause a noticeable performance loss.
4.2.5 THERMTRIP_N Signal
Regardless of whether Adaptive Thermal Monitor is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached an elevated temperature (refer to the THERMTRIP_N definition in
Section 5, “Signal Descriptions”). At this point, the THERMTRIP_N signal will go active
and stay active. THERMTRIP_N activation is independent of processor activity and does
not generate any Intel®
QuickPath Interconnect transactions. If THERMTRIP_N is
asserted, all processor supplies must be removed within the timeframe provided in
Table 6-28. The temperature at which THERMTRIP_N asserts is not user configurable
and is not software visible.
4.2.6 Integrated Memory Controller (IMC) Thermal Features
4.2.6.1 DRAM Throttling Options
The Integrated Memory Controller (IMC) has an independent mechanism that can
cause system memory throttling:
• Closed Loop Thermal Throttling (CLTT)
4.2.6.1.1 Closed Loop Thermal Throttling (CLTT)
The processor periodically samples temperatures from the DIMM TSoD devices over a
programmable interval. The PCU determines the hottest DIMM rank from TSoD data
and informs the integrated memory controller for use in bandwidth throttling decisions.
4.2.6.2 MEM_HOT_C01_N and MEM_HOT_C23_N Signal
The processor includes a pair of new bi-directional memory thermal status signals
useful for manageability schemes. Each signal presents and receives thermal status for
a pair of memory channels (channels 0 & 1 and channels 2 & 3).
• Input Function: The processor can periodically sense the MEM_HOT_{C01/C23}_N
signals to detect if the platform is requesting a memory throttling event.
Manageability hardware could drive this signal due to a memory voltage regulator
thermal or electrical issue or because of a detected system thermal event (for
example, fan is going to fail) other system devices are exceeding their thermal
target. The input sense period of these signals are programmable,100 us is the
default value. The input sense assertion time recognized by the processor is
programmable, 1us is the default value. See Table 6-28, for more timing
information. If the sense assertion time is programmed to zero, then the processor
ignores all external assertions of MEM_HOT_{C01/C23}_N signals (in effect they
become outputs).
• Output Function: The output behavior of the MEM_HOT_{C01/C23}_N signals
supports Level mode. In this mode, MEM_HOT_{C01/C23}_N event temperatures
are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI
threshold settings in the iMC. In Level mode, when asserted, the signal indicates to
the platform that a BIOS-configured thermal threshold has been reached by one or
more DIMMs in the covered channel pair.