Vol 1

Power Management

38 Intel® Xeon® Product 2800/4800/8800 v2 Product Family

Datasheet Volume One, February 2014

— If the break event is masked, the processor attempts to re-enter its previous

package state.

• If the break event was due to a memory access or snoop request.

— But the platform did not request to keep the processor in a higher package

C-state, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or snoop

request is serviced and the package remains in the higher power C-state.

The package C-states fall into two categories: independent and coordinated. C0/C1 are

independent, while C3/C6 are coordinated across processors.

Package C-states are based on exit latency requirements which are accumulated from

the PCIe* devices, PCH, and software sources. The level of power savings that can be

achieved is a function of the exit latency requirement from the platform. As a result,

there is no fixed relationship between the coordinated C-state of a package, and the

power savings that will be obtained from the state. Coordinated package C-states offer

a range of power savings which is a function of the guaranteed exit latency requirement

from the platform.

There is also a concept of Execution Allowed (EA), when EA status is 0, the cores in a

socket are in C3 or a deeper state, a socket initiates a request to enter a coordinated

package C-state. The coordination is across all sockets and the PCH.

Table 3-9 shows an example of a dual-core processor package C-state resolution.

Figure 3-3 summarizes package C-state transitions with package C2 as the interim

between PC0 and PC1 prior to PC3 and PC6. Note that this is only an interim state.

Table 3-9. Coordination of Core Power States at the Package Level

Package C-State

Core 1

C0 C1 C3 C6

Core 0

C0 C0 C0 C0

C0 C1

1. The package C-state will be C1E if all actives cores have resolved a core C1 state or higher.

C0 C1

C3 C3

C0 C1

C3 C6