Vol 1

PIROM
168 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
9.2 SMBus Memory Component Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of
the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the
SKTID[1:0] pins. Note that SKTID[2] does not affect the SMBus address for the
memory component. These address pins are pulled down weakly (10 k) on the
processor substrate to ensure that the memory components are in a known state in
systems which do not support the SMBus (or only support a partial implementation).
The “Z” bit is the read/write bit for the serial bus transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be
generated by an SMBus master.
Table 9-3 describes the address pin connections and how they affect the addressing of
the memory component.
Note:
1. This addressing scheme will support up to 4 processors on a single SMBus.
9.3 Managing Data in the PIROM
The PIROM consists of the following sections:
•Header
• Processor Data
• Processor Core Data
• Processor Uncore Data
•Cache Data
•Package Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data
Details on each of these sections are described below.
Table 9-3. Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
1
Device Select R/W
Bits 7-4 SKTID[2]
SKTID[1]
Bit 2
SKTID[0]
Bit 1
Bit 0
A0h/A1h 10100 10100 0 0 X
A2h/A3h 10100 10100 0 1 X
A4h/A5h 10100 10100 1 0 X
A6h/A7h 10100 10100 1 1 X