Update

10 Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families
November 2014 Specification Update
Specification Changes
BP33. XNo FixPackage C3/C6 with Memory Self-refresh Enabled May Cause False Error Logging
BP34. XNo FixPerformance Monitor WOKEN Event May Under Count
BP35. XNo FixPECI Command Average Temperature Read does not report correct Temperature
BP36. XNo FixIntel
®
QPI Initialization May Cause a CATERR During Power-on Reset
BP37. XNo Fix
EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service
Routine
BP38. XNo FixA First Level Data Cache Parity Error May Result in Unexpected Behavior
BP39. XNo Fix
An Unexpected Page Fault or EPT Violation May Occur After Another Logical Processor Creates a
Valid Translation for a Page
BP40. XNo FixA Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or PDPTE
BP41. XNo FixIO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
BP42. XNo FixWriting an Illegal Vector to the IA32_X2APIC_SELF_IPI MSR Will Hang the Processor
BP43. XNo FixSuccessive Fixed Counter Overflows May be Discarded
BP44. XNo Fix
VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry to the Shutdown
State
BP45. XNo Fix
Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-Bit Linear
Addresses
BP46. XNo Fix
A Combination of Data Accesses That Are Split Across Cacheline Boundaries May Lead to a
Processor Hang
BP47. XNo FixA Load May Appear to be Ordered Before an Earlier Locked Instruction
BP48. XNo FixVMRESUME May Omit Check of Revision Identifier of Linked VMCS
BP49. XNo FixAPIC Timer Interrupts May be Lost During Core C3
BP50. XNo FixMCI_ADDR May be Incorrect For Cache Parity Errors
BP51. XNo FixCR0.CD Is Ignored in VMX Operation
BP52. XNo Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with
Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering
Violations
BP53. XNo Fix
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error
is Logged
BP54. XNo FixThe Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging
BP55. XNo FixEPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly
BP56. XNo Fix
IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest Index Value Used
For VMCS Encoding
BP57. XNo FixVirtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System Crash
BP58. XNo FixVM Exit May Set IA32_EFER.NXE When IA32_MISC_ENABLE Bit 34 is Set to 1
BP59. XNo FixPerformance Monitor Counter MEM_INST_RETIRED.STORES May Count Higher than Expected
Number SPECIFICATION CHANGES
SCh1.
Correction to Product Families Features
Table 1. Errata Table (Sheet 2 of 2)
Number
Stepping
Status Description
A-2