Hub Datasheet

94 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.6.24 DRAM_FERR—DRAM First Error Register (D0:F1)
Address Offset: 80h
Default Value: 00h
Sticky Yes
Attribute: RO, R/WC
Size: 8 bits
This register stores the FIRST ECC error on the DRAM interface. Only 1 error bit will be set in this
register. Any future errors (NEXT errors) will be set in the DRAM_NERR Register. No further
error bits in this register will be set until the existing error bit is cleared.
Note: Software must write a 1 to clear bits that are set.
3.6.25 DRAM_NERR—DRAM Next Error Register (D0:F1)
Address Offset: 82h
Default Value: 00h
Sticky Yes
Attribute: RO, R/WC
Size: 8 bits
The FIRST memory ECC error will be stored in the DRAM_FERR Register. This register stores all
future memory ECC errors. Multiple bits in this register may be set.
Note: Software must write a 1 to clear bits that are set.
Bits
Default,
Access
Description
7:2 Reserved
1
0b
R/WC
Uncorrectable Memory Error Detected.
0 = No uncorrectable memory error detected.
1 = MCH detected an ECC error on the memory interface that is not correctable.
0
0b
R/WC
Correctable Memory Error Detected.
0 = No correctable memory error detected.
1 = MCH detected and corrected an ECC error on the memory interface.
Bits
Default,
Access
Description
7:2 Reserved
1
0b
R/WC
Uncorrectable Memory Error Detected.
0 = No uncorrectable memory error detected.
1 = The MCH has detected an ECC error on the memory interface that is not correctable.
0
0b
R/WC
Correctable Memory Error Detected.
0 = No correctable memory error detected.
1 = The MCH has detected and corrected an ECC error on the memory interface.