Hub Datasheet

86 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.6.14 HIA_FERR—HI_A First Error Register (D0:F1)
Address Offset: 50h
Default Value: 00h
Sticky Yes
Attribute: RO, R/WC
Size: 8 bits
This register stores the first error related to the HI_A interface. Only 1 error bit will be set in this
register. Any future errors (NEXT errors) will be set in the HIA_NERR Register. No further error
bits in this register will be set until the existing error bit is cleared.
Note: Software must write a 1 to clear bits that are set.
Bits
Default,
Access
Description
7 Reserved
6
0b
R/WC
HI A Target Abort (TAHLA).
0 = No Target Abort on MCH originated HI_A cycle detected.
1 = MCH detected that an MCH originated HI_A cycle was terminated with a Target
Abort.
5 Reserved
4
0b
R/WC
HI_A Data Parity Error Detected.
0 = No data parity error detected.
1 = MCH detected a parity error on a HI_A data transfer.
3:1 Reserved
0
0b
R/WC
HI_A Address/Command Error Detected.
0 = No address or command parity error detected.
1 = MCH detected a parity error on a HI_A address or command.