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Intel

E7505 Chipset MCH Datasheet 81

3.6.3 PCICMD—PCI Command Register (D0:F1)

Address Offset: 04–05h

Default Value: 0000h

Sticky No

Attribute: RO, R/W

Size: 16 bits

Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented.

3.6.4 PCISTS—PCI Status Register (D0:F1)

Address Offset: 06–07h

Default Value: 0000h

Sticky No

Attribute: RO/R/W

Size: 16 bits

PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI

interface. Bit 14 is read/write clear. All other bits are Read Only. Since MCH Device 0 does not

physically reside on PCI_A, many of the bits are not implemented.

Bits

Default,

Access

Description

15:9 Reserved

R/W

SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR messaging.

The MCH does not have an SERR signal. The MCH communicates the SERR condition

by sending an SERR message over HI_A to the Intel

ICH4.

0 = Disable. SERR message is not generated by the MCH for Device 0.

1 = Enable. MCH generates SERR messages over HI_A for specific Device 0 error

conditions that are individually enabled in the SERRCMD_HI, SERRCMD_SB, and

SERRCMD_DRAM registers. The error status is reported in the FERR register /

NERR register and PCISTS registers.

7:0 Reserved

Bits

Default,

Access

Description

15 Reserved

R/WC

Signaled System Error (SSE). Software clears this bit by writing a 1 to it.

0 = MCH Device 0 did Not generate an SERR message over HI_A.

1 = MCH Device 0 generated an SERR message over HI_A for any enabled Device 0

error condition. Device 0 error conditions are enabled in the PCICMD and

SERRCMD_HI, SERRCMD_SB, and SERRCMD_DRAM registers. Device 0 error

flags are read/reset from the PCISTS or Error registers.

13:0 Reserved