Hub Datasheet
72 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.28 AGPCMD—AGP Command Register (D0:F0)
Address Offset: A8–ABh
Default Value: 0000 0000h
Attribute: R/W
Size: 32 bits
This register provides control of the AGP operational parameters. Set by drivers.
Bits
Default,
Access
Description
31:13 Reserved
12:10
000b
RO
Programmed Calibration Period (PCAL_Cycle).
000 = 4 ms
9
0b
R/W
Side Band Addressing Enable (SBAEN).
0 = Disable.
1 = Enable. In AGP 3.0 signaling mode this bit is ignored as sideband addressing is
the only allowed mechanism.
8
0b
R/W
AGP Enable (AGPEN).
0 = Disable. MCH ignores all AGP. operations, including the sync cycle. Any AGP
operations received while this bit is set to 1 will be serviced even if this bit is reset
to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA
command being delivered in 1x mode the command will be issued.
1 = Enable. MCH responds to AGP. operations delivered via PIPE#, or to operations
delivered via SBA if the AGP side band enable bit is also set to 1.
7:6 Reserved
5
0b
RO
Greater Than Four Gigabyte Enable (GT4GIG). Hardwired to 0. The MCH, as an
AGP target, does not support addressing greater than 4 GB.
4
0b
R/W
Fast Write Enable (FWEN).
0 = Disable. When this bit is 0 or the data rate bits are set to 1x mode, the memory
write transactions from the MCH to the AGP master uses standard PCI protocol.
1 = Enable. MCH uses the Fast Write protocol for memory write transactions from the
MCH to the AGP master. Fast Writes will occur at the data transfer rate selected
by the data rate bits (2:0) in this register.
3 Reserved
2:0
000b
R/W
Data Rate Enable (DRATE). The setting of these bits determines the AGP data
transfer rate. One (and only one) bit in this field must be set to indicate the desired
data transfer rate. The same bit must be set on both master and target.The encoding is
determined by the AGP 3.0 signaling mode bit in the AGPSTAT register.
Encoding
AGP Specification 2.0
Signaling
AGP Specification 3.0
Signaling
001 1x Transfer Mode 4x Transfer Mode
010 2x Transfer Mode 8x Transfer Mode
100 4x Transfer Mode reserved