Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 57
Register Description
Figure 3-1. PAM Registers
Table 3-3. PAM Associated Attribute Bits
PAM Reg Attribute Bits Memory Segment Comments Offset
PAM0 3:0, 7:6 Reserved — — 59h
PAM0 5:4 R R WE RE 0F0000h–0FFFFFh BIOS Area 59h
PAM1 3:2, 7:6 — — — — — Reserved 5Ah
PAM1 1:0 R R WE RE 0C0000h–0C3FFFh BIOS Area 5Ah
PAM1 5:4 R R WE RE 0C4000h–0C7FFFh BIOS Area 5Ah
PAM2 3:2, 7:6 — — — — — Reserved 5Bh
PAM2 1:0 R R WE RE 0C8000h–0CBFFFh BIOS Area 5Bh
PAM2 5:4 R R WE RE 0CC000h–0CFFFFh BIOS Area 5Bh
PAM3 3:2, 7:6 — — — — — Reserved 5Ch
PAM3 1:0 R R WE RE 0D0000h–0D3FFFh BIOS Area 5Ch
PAM3 5:4 R R WE RE 0D4000h–0D7FFFh BIOS Area 5Ch
PAM4 3:2, 7:6 — — — — — Reserved 5Dh
PAM4 1:0 R R WE RE 0D8000h–0DBFFFh BIOS Area 5Dh
PAM4 5:4 R R WE RE 0DC000h–0DFFFFh BIOS Area 5Dh
PAM5 3:2, 7:6 — — — — — Reserved 5Eh
PAM5 1:0 R R WE RE 0E0000h–0E3FFFh BIOS Extension 5Eh
PAM5 5:4 R R WE RE 0E4000h–0E7FFFh BIOS Extension 5Eh
PAM6 3:2, 7:6 — — — — — Reserved 5Fh
PAM6 1:0 R R WE RE 0E8000h–0EBFFFh BIOS Extension 5Fh
PAM6 5:4 R R WE RE 0EC000h–0EFFFFh BIOS Extension 5Fh
PAM6 5Fh
PAM1
PAM2
PAM3
PAM4
PAM5
5Ah
5Bh
5Ch
5Dh
5Eh
Offset
WERRRER WE RER
70123456
Reserved
Reserved
W rite Enable (R/W )
1 = Enable
0 = Disable
Read Enable (R/W )
1 = Enable
0 = Disable
Reserved
Reserved
Write Enable (R/W)
1 = Enable
0 = Disable
Read Enable (R/W)
1 = Enable
0 = Disable
59hPAM0
HI Segment LO Segment
Reserved