Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 55

R/W

Throttled-Write Occurred.

0 = This bit is cleared by writing a 0 to it.

1 = This bit is set when a write is throttled. This bit is set when the maximum allowed

number of writes has been reached during a time-slice and there is at least one

more write to be done.

R/W

Throttled-Read Occurred.

0 = This bit is cleared by writing a 0 to it.

1 = This bit is set when a read is throttled. This bit is set when the maximum allowed

number of reads has been reached during a time-slice and there is at least one

more read to be done.

loaded from

HA7# on

RESET#

In-Order Queue Depth (IOQD). This bit reflects the value sampled on HA7# on the

deassertion of the CPURST#. It indicates the depth of the processor bus in-order

queue (i.e., level of processor bus pipelining).

0 = When IOQD is set to 0 (HA7# is sampled asserted; i.e., 1; or an electrical low),

the depth of the IOQ is set to 1 (i.e., no pipelining support on the processor bus).

HA7# may be driven low during CPURST# by an external source.

1 = When IOQD is set to 1 (HA7# sampled as 0; an electrical high), the depth of the

processor bus in-order queue is configured to the maximum allowed by the

processor protocol (i.e., 12).

1:0 Reserved

Bits

Default,

Access

Description