Hub Datasheet

2
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3.5.21 REROTC—Receive Enable Reference Output Timing Control Register
(D0:F0)66
3.5.22 CLOCK_DIS—CK/CK# Clock Disable Register (D0:F0) .................. 66
3.5.23 DDR_CNTL—DDR Memory Control Register (D0:F0) ..................... 67
3.5.24 SMRAM—System Management RAM Control Register (D0:F0)...... 68
3.5.25 ESMRAMC—Extended System Management RAM Control Register
(D0:F0)69
3.5.26 ACAPID—AGP Capability Identifier Register (D0:F0) ...................... 70
3.5.27 AGPSTAT—AGP Status Register (D0:F0) ....................................... 70
3.5.28 AGPCMD—AGP Command Register (D0:F0).................................. 72
3.5.29 AGPCTRL—AGP Control Register (D0:F0)...................................... 73
3.5.30 APSIZE—Aperture Size Register (D0:F0) ........................................ 74
3.5.31 ATTBASE—Aperture Translation Table Register (D0:F0)................ 75
3.5.32 AMTT—AGP MTT Control Register (D0:F0) .................................... 75
3.5.33 LPTT—AGP Low Priority Transaction Time Register (D0:F0).......... 76
3.5.34 TOLM—Top of Low Memory Register (D0:F0) ................................. 77
3.5.35 REMAPBASE—Remap Base Address Register (D0:F0) ................. 77
3.5.36 REMAPLIMIT—Remap Limit Address Register (D0:F0) .................. 78
3.5.37 SKPD—Scratch Pad Data Register (D0:F0)..................................... 78
3.5.38 DVNP—Device Not Present Register (D0:F0).................................. 78
3.6 Chipset Host RAS Controller Registers
(Device 0, Function 1)79
3.6.1 VID—Vendor Identification Register (D0:F1).................................... 80
3.6.2 DID—Device Identification Register (D0:F1) .................................... 80
3.6.3 PCICMD—PCI Command Register (D0:F1) ..................................... 81
3.6.4 PCISTS—PCI Status Register (D0:F1)............................................. 81
3.6.5 RID—Revision Identification Register (D0:F1).................................. 82
3.6.6 SUBC—Sub-Class Code Register (D0:F1)....................................... 82
3.6.7 BCC—Base Class Code Register (D0:F1) ....................................... 82
3.6.8 MLT—Master Latency Timer Register (D0:F1)................................. 83
3.6.9 HDR—Header Type Register (D0:F1) .............................................. 83
3.6.10 SVID—Subsystem Vendor Identification Register (D0:F1)............... 83
3.6.11 SID—Subsystem Identification Register (D0:F1).............................. 83
3.6.12 FERR_GLOBAL—Global First Error Register (D0:F1) ..................... 84
3.6.13 NERR_GLOBAL—Global Next Error Register (D0:F1) .................... 85
3.6.14 HIA_FERR—HI_A First Error Register (D0:F1) ................................ 86
3.6.15 HIA_NERR—HI_A Next Error Register (D0:F1) ............................... 87
3.6.16 SCICMD_HIA—SCI Command Register (D0:F1)............................. 87
3.6.17 SMICMD_HIA—SMI Command Register (D0:F1) ............................ 88
3.6.18 SERRCMD_HIA—SERR Command Register (D0:F1)..................... 88
3.6.19 SB_FERR—System Bus First Error Register (D0:F1)...................... 89
3.6.20 SB_NERR—System Bus Next Error Register (D0:F1) ..................... 90
3.6.21 SCICMD_SB—SCI Command Register (D0:F1) .............................. 91
3.6.22 SMICMD_SB—SMI Command Register (D0:F1) ............................. 92
3.6.23 SERRCMD_SB—SERR Command Register (D0:F1) ...................... 93
3.6.24 DRAM_FERR—DRAM First Error Register (D0:F1)......................... 94
3.6.25 DRAM_NERR—DRAM Next Error Register (D0:F1)........................ 94
3.6.26 SCICMD_DRAM —SCI Command Register (D0:F1) ....................... 95
3.6.27 SMICMD_DRAM—SMI Command Register (D0:F1)........................ 95
3.6.28 SERRCMD_DRAM—SEER Command Register (D0:F1)................. 96
3.6.29 DRAM_CELOG_ADD—DRAM First Correctable Memory Error Ad-
dress Register (D0:F1)96