Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 21
Signal Description
Signal Description 2
This chapter provides a detailed description of MCH signals. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. When “#” is not present after the signal name, the signal is
asserted when at a high voltage level.
The following notations are used to describe the signal type:
I Input pin
O Output pin
I/O Bidirectional Input/Output pin.
s/t/s Sustained tri-state. This pin is driven to its inactive state prior to tri-stating.
as/t/s Active Sustained tri-state. This applies to some of the hub interface signals. This pin is
weakly driven to its last driven value.
2x Double-pump clocking. Addressing at 2x of HCLK
4x Quad-pump clocking. Data transfer at 4x of HCLK
The signal description also includes the type of buffer used for the particular signal:
AGTL+ The processor’s system buses use a technology called AGTL+, or Assisted
Gunning Transceiver Logic. AGTL+ buffers are open-drain and require pull-up
resistors to provide the high logic level and termination. AGTL+ output buffers
differ from GTL+ buffers with the addition of an active pMOS pull-up
transistor to assist the pull-up resistors during the first clock of a low-to-high
voltage transition.
Asynchronous
AGTL+
Intel Xeon processors with 533 MHz Sysytem Bus and with 512-KB L2 cache
do not utilize CMOS voltage levels on any signals that connect to the
processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize
GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals
(THERMTRIP# and PROCHOT#) utilize GTL+ output buffers. All of these
signals follow the same DC requirements as AGTL+ signals, however the
outputs are not actively driven high (during a logical 0 to 1 transition) by the
processor (the major difference between GTL+ and AGTL+). These signals do
not have setup or hold time specifications in relation to HCLKINx. However,
all of the asynchronous GTL+ signals are required to be asserted for at least two
HCLKINx in order for the processor to recognize them.
CMOS CMOS buffers. System bus address and data bus signals are logically inverted
signals. The logical values are the inversion of the electrical values on the
system bus. A signal “#” indicates an active low, and with no “#” indicates an
active high.
AGP AGP interface signals. These signals are compatible with AGP 2.0 (1.5 V)
signaling and AGP 3.0 (0.8 V) Signaling Environment Specifications (AC and
DC). These buffers are not 3.3 V tolerant.
SSTL-2 Stub Series Terminated Logic for 2.5 V (DDR interface).
HI2 Buffer Hub Interface buffer types