Hub Datasheet

164 Intel
®
E7505 Chipset MCH Datasheet
Functional Description
5.4.12 Fast Writes
The Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target.
This type of access is required to pass data/control directly to the AGP master instead of placing
the data into main memory and then having the AGP master read the data. For 1x transactions, the
protocol follows the PCI bus specification. However, for higher speed transactions (2x, 4x, or 8x),
FW transactions follow a combination for PCI and AGP bus protocols for data movement.
5.4.13 AGP Connector
The MCH only supports the AGP 1.5 V connector that permits a 1.5 V AGP 2.0 or AGP 3.0
graphics card to be supported by the system. The MCH is a “Universal AGP 8x” device supporting
either 1.5 V or 0.8 V signaling. A keep-out keying mechanism in the AGP 1.5 V connector
prevents a 3.3 V card from inadvertently being installed.
5.4.14 PCI Semantic Transactions on AGP
The MCH accepts and generates PCI semantic transactions on the AGP bus. The MCH guarantees
that PCI semantic accesses to DRAM are kept coherent with the processor caches by generating
snoops to the processor bus.