Hub Datasheet

110 Intel

E7505 Chipset MCH Datasheet

3.7.19 MLIMIT1—Memory Limit Address Register (D1:F0)

Address Offset: 22–23h

Default Value: 0000h

Attribute: R/W, RO

Size: 16 bits

This register controls the processor-to-AGP non-prefetchable memory access routing based on the

following formula:

MEMORY_BASE ≤ address ≤ MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20

of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.

This register must be initialized by the configuration software. For the purpose of address decode,

address bits A19:0 are assumed to be FFFh. Thus, the top of the defined memory address range will

be at the top of a 1-MB aligned memory block.

Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable AGP

address ranges (typically where control/status memory-mapped I/O data structures of the graphics

controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges

(typically graphics local memory). This segregation allows application of USWC space attribute to

be performed in a true plug-and-play manner to the prefetchable address range for improved

processor-to-AGP memory access performance.

Note: Configuration software is responsible for programming all address range registers (prefetchable,

non-prefetchable) with the values that provide exclusive address ranges (prevent overlap with each

other and/or with the ranges covered with the main memory). There is no provision in the MCH

hardware to enforce prevention of overlap and operations of the system in the case of overlap are

not guaranteed.

Bits

Default,

Access

Description

15:4

000h

R/W

Memory Address Limit (MLIMIT). These bits corresponds to A31:20 of the memory

address that corresponds to the upper limit of the range of memory accesses that will

be passed by the device 1 bridge to AGP.

3:0 Reserved