Datasheet

Datasheet 79
DRAM Controller Registers (D0:F0)
5.1.18 PAM1—Programmable Attribute Map 1
B/D/F/Type: 0/0/0/PCI
Address Offset: 91h
Default Value: 00h
Access: RO, RW/L
Size: 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h – 0C7FFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 RW/L 00b
0C4000h–0C7FFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
3:2 RO 00b Reserved
1:0 RW/L 00b
0C0000h–0C3FFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.