Specification Update

Intel
®
Xeon
®
Processor 7000 Series 31
Specification Update, March 2010
A45. Data access which spans both canonical and non-canonical address
space may hang system
Problem: If a data access causes a page split across the canonical to non-canonical address
space, the processor may livelock which in turn would cause a system hang.
Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel
has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A46. Running in SMM and L1 data cache adaptive mode may cause
unexpected system behavior when SMRAM is mapped to cacheable
memory
Problem: In a Hyper-Threading Technology-enabled system, unexpected system behavior may
occur if a change is made to the value of the CR3 result from an RSM (Resume from
System Management) instruction while in L1 data cache adaptive mode
(IA32_MISC_ENABLES MSR 0x1a0, bit 24). This behavior will only be visible when
SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit.
Implication: This erratum can have multiple failure symptoms, including incorrect data in memory.
Intel has not observed this erratum with any commercially available software.
Workaround: Disable L1 data cache adaptive mode by setting the L1 Data Cache Context Mode
control bit (bit 24) of the IA32_MISC_ENABLES MSR (0x1a0) to 1. It is possible for the
BIOS to contain a workaround for this erratum
Status: For the steppings affected, see the Summary Table of Changes.
A47. A 64-bit value of linear instruction pointer (LIP) may be reported
incorrectly in the branch trace store (BTS) memory record or in the
precise event based sampling (PEBS) memory record
Problem: On a processors supporting Intel EM64T:
• If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the
64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will be
set to 0xFFFFFFFF when they should be 0).
• If a PEBS event occurs on an instruction whose last byte is at memory location
FFFFFFFFh, the 64-bit value of LIP in the PEBS record will be incorrect (upper 32
bits will be set to FFFFFFFFh when they should be 0).
Implication: Intel has not observed this erratum on any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A48. PDE/PTE Loads and continuous locked updates to the same cache line
may cause a system livelock
Problem: In a multiprocessor configuration, if one processor is continuously doing locked updates
to a cache line that is being accessed by another processor doing a page table walk, the
page table walk may not complete.
Implication: Due to this erratum, the system may livelock until some external event interrupts the
locked update. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.