Specification Update

16 Intel
®
Xeon
®
Processor 7000 Series
Specifiication Update, March 2010
A60 X Plan Fix Exit qualification and pending debug exceptions Virtual-Machine Control Structure
(VMCS) fields contain incorrect information on VM exits due to debug exceptions
A61 X Plan Fix VM exit saves incorrect interruptibility state information on exit due to nested
exceptions
A62 X Plan Fix VM exit on Load Machine Status Word (LMSW) may not show expected exit
information in the Virtual-Machine Control Structure (VMCS)
A63 X Plan Fix An incorrect load may be issued under conditions which cause VM exit
A64 X Plan Fix A Start-up IPI (SIPI) VM exit does not clear pending INITs
A65 X No Fix Access to an unsupported address range in uniprocessor (UP) or dual processor
(DP) systems supporting Intel® Virtualization Technology may not trigger
appropriate actions
A66 X No Fix VM exit due to a MOV from CR8 may cause an unexpected memory access
A67 X No Fix The processor may incorrectly respond to machine checks during VM entry/exit
transitions
A68 X No Fix NIT during string operations in the Virtual-Machine Extension (VMX) guest mode
may cause unexpected system behavior
A69 X No Fix Power down requests may not be serviced if a power down transition is interrupted
by an in-target probe event in the presence of a specific type of VM exit
A70 X No Fix VM entry/exit writes to LSTAR/SYSCALL_FLAG MSRs may cause incorrect data
to be written to bits [63:32]
A71 X No Fix VM exit due to TPR shadow below threshold may improperly set and cause
“Blocking by STI” actions
A72 X Plan Fix VM exit on Load Machine Status Word (LMSW) may not show expected exit
information in the Virtual-Machine Control Structure (VMCS)
A73 X Plan Fix A VM exit may occur when the processor is in wait-for-SIPI or shutdown states and
a chipwide power down transition occurs
A74 X No Fix The execution of a VMPTRLD instruction may cause an unexpected memory
access
A75 X No Fix The execution of VMPTRLD or VMREAD may cause an unexpected memory
access
A76 X Plan Fix Attempting to use an LDT entry when the LDTR has been loaded with an unusable
segment may cause unexpected memory accesses
A77 X No Fix FS/GS base MSRs can be loaded from MSR-load areas during VM entry or VM exit
A78 X Plan Fix NMI-blocking information recorded in VMCS may be incorrect after a #GP on an
IRET instruction
A79 X Plan Fix VMLAUNCH/VMRESUME may not fail when VMCS is programmed to cause VM
exit to return to a different mode
A80 X No Fix VMCALL to activate dual-monitor treatment of SMIS and SMM ignores reserved bit
settings in VM-exit control field
A81 X No Fix Using 2M/4M pages when A20M# is asserted may result in incorrect address
translations
A82 X No Fix Writing shared unaligned data that crosses a cache line without proper
semaphores or barriers may expose a memory ordering issue
A83 X No Fix Processor may hang during entry into No-Fill Mode or No-Eviction Mode
A84 X No Fix FPU operand pointer may not be cleared following FINIT/FNINIT
Table 2. Errata (Sheet 4 of 5)
Number A-0 Status Description