Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 93
Register Description
3.6.23 SERRCMD_SB—SERR Command Register (D0:F1)
Address Offset: 6Ch
Default Value: 00h
Sticky No
Attribute: R/W
Size: 8 bits
This register determines whether SERR will be generated when the associated flag is set in either
the SB_FERR or SB_NERR Register. When an error flag is set in the SB_FERR or SB_NERR
Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or
SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
Description
7
0b
R/W
SERR on System Bus BINIT# Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 7 is set in SB_FERR or SB_NERR
6
0b
R/W
SERR on System Bus xERR# Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 6 is set in SB_FERR or SB_NERR
5
0b
R/W
SERR on Non-DRAM Lock Error Enable.
0 = No SERR generation
1 = Generate SERR if bit 5 is set in SB_FERR or SB_NERR
4
0b
R/W
SERR on System Bus Address Above TOM Enable.
0 = No SERR generation
1 = Generate SERR if bit 4 is set in SB_FERR or SB_NERR
3
0b
R/W
SERR on System Bus Data Parity Error Enable.
0 = No SERR generation
1 = Generate SERR if bit 3 is set in SB_FERR or SB_NERR
2
0b
R/W
SERR on System Bus Address Strobe Glitch Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 2 is set in SB_FERR or SB_NERR
1
0b
R/W
SERR on System Bus Data Strobe Glitch Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 1 is set in SB_FERR or SB_NERR
0
0b
R/W
SERR on System Bus Request/Address Parity Error Enable.
0 = No SERR generation
1 = Generate SERR if bit 0 is set in SB_FERR or SB_NERR