Hub Datasheet
Intel
®
E7505 Chipset MCH Datasheet 71
Register Description
5
0b
RO
Greater Than Four Gigabyte Support (GT4GIG). Hardwired to 0. The MCH does not
support addresses greater than 4 GB.
4
1b
RO
Fast Write Support (FW). Hardwired to a 1. The MCH supports Fast Writes from the
processor to the AGP master. It is
3
xb
RO
AGP 3.0 Signaling Mode. This bit is set by the hardware on reset based on the AGP
8x detection via the VREF Comparator.
0 = AGP 2.0 signaling mode (1.5 V).
1 = Graphics card is AGP 8x mode.
2:0
111b or
01xb
RO
Data Rate Support (RATE). The value of this field is determined by the AGP 3.0
signaling mode bit above.
In AGP 3. 0 signaling mode (AGP 3.0 signaling mode bit = 1), these bits are 01X,
indicating that 8x mode is supported. A 1 indicates that the 4x data rate is supported in
8x mode.
In AGP 2.0 signaling mode, these bits are 111 indicating that 1x, 2x, and 4x modes are
all supported.
Signaling mode is determined by bit 3 (AGP 3.0 signaling mode bit) above.
Bits
Default,
Access
Description
2.0 Signaling (1.5 V) Bit 2 Bit 1 BIt 0
Data Rate 4x 2x 1x
MCH Value 1 (supported) 1 (supported) 1 (supported)
3.0 Signaling (0.8 V) Bit 2 Bit 1 BIt 0
Data Rate reserved 8x 4x
MCH value 0 1 (supported) Programmable by
BIOS