Hub Datasheet

40 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.2 PCI Configuration Space Access
The MCH and the ICH4 are physically connected by HI_A. From a configuration standpoint, HI_A
is logically PCI bus #0. As a result, all devices internal to the MCH and ICH4 appear to be on PCI
bus #0. The system’s primary PCI expansion bus is physically attached to the ICH4 and, from a
configuration perspective appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and
therefore has a programmable PCI Bus number.
Note: The primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a
configuration standpoint.
The 16-bit hub interface ports appear to system software to be real PCI buses behind PCI-to-PCI
bridges resident as devices on PCI bus #0. The MCH decodes multiple PCI Device numbers. The
configuration registers for the devices are mapped as devices residing on PCI bus #0. Each Device
Number may contain multiple functions.
• Device 0: Chipset Host Controller. Logically device 0 appears as a PCI device residing on PCI
bus #0. Physically, device 0 contains the standard PCI registers, DRAM controller registers,
HI_A registers, and other MCH specific registers.
• Device 1: Host-to-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge
residing on PCI bus #0. Physically Device 1 contains the standard PCI-to-PCI bridge registers
and the standard AGP/PCI configuration registers (including the AGP I/O and memory
address mapping).
• Device 2: Host-to-HI_B Bridge. Logically this bridge appears to be a PCI-to-PCI bridge
device residing on PCI bus #0. Physically, Device 2 contains the standard PCI registers and
configuration registers for HI_B.
Table 3-1 shows the device number assignment for the various internal MCH devices:
Reserved
Registers
In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host-hub interface Bridge/DRAM Controller and the internal
graphics device entities that are marked either “Reserved” or Intel Reserved.” When a
“Reserved” register location is read, a random value can be returned. (“Reserved” registers
can be 8, 16, or 32 bits in size). Registers that are marked as “Reserved” must not be
modified by system software. Writes to “Reserved” registers may cause system failure.
Default Value
Upon Reset
Upon a full reset, the MCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping options.
The default state represents the minimum functionality feature set required to successfully
bring up the system. Hence, it does not represent the optimal system configuration. It is the
responsibility of the system initialization software (usually BIOS) to properly determine the
DRAM configurations, operating parameters, and optional system features that are
applicable, and to program the MCH registers accordingly.
Term Description
Table 3-1. MCH Logical Configuration Resources
MCH Function Device #, Function #
Chipset Host Controller Device 0, Function 0
Chipset Host RAS Controller Device 0, Function 1
Host-to-AGP Bridge (16 bit PCI-to-PCI) Device 1, Function 0
Host-to-HI_B Bridge Controller (16 bit PCI-to-PCI) Device 2, Function 0
Host-to-HI_B Bridge Error Reporting (16 bit PCI-to-PCI) Device 2, Function 1