Hub Datasheet

Signal Description
36 Intel
®
E7505 Chipset MCH Datasheet
GTRDY# (2.0),
GTRDY (3.0)
I/O
s/t/s
AGP
Target Ready: This signal is used for both GFRAME(#) based and AGP
transactions. During AGP transactions, it indicates the AGP compliant target is
ready to provide read data for the entire transaction (when the transfer size is
less than or equal to 32 bytes) or is ready to transfer the initial or subsequent
block (32 bytes) of data when the transfer size is greater than 32 bytes. The
target is allowed to insert wait-states after each block (32 bytes) is transferred
on both read and write transactions.
GSTOP# (2.0),
GSTOP (3.0)
I/O
s/t/s
AGP
STOP: This signal is used during GFRAME(#) based transactions by the target
to request that the master stop the current transaction. This signal is not used
during AGP transactions.
RBF# (2.0),
RBF (3.0)
I/O
s/t/s
AGP
Read Buffer Full: This signal indicates if the master is ready to accept
previously requested low priority read data. When RBF(#) is asserted, the MCH
is not allowed to return low priority read data to the AGP master on the first
block. RBF(#) is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data, then it is not
required to implement this signal.
WBF# (2.0),
WBF (3.0
I
AGP
Write Buffer Full: This signal indicates if the master is ready to accept Fast
Write data from the MCH. When WBF(#) is asserted, the MCH is not allowed to
drive Fast Write data to the AGP master. WBF(#) is only sampled at the
beginning of a cycle.
If the AGP master is always ready to accept fast write data, it is not required to
implement this signal.
SERR# (2.0),
SERR (3.0)
I
AGP
Serious Error: The AGP master may assert this signal to indicate an address
parity error or other serious error. The master asserts the signal for one clock,
then float it. When enabled, the SERR will be passed onto the Intel
®
ICH4 as an
SERR message on the HI_A. The enable bit is in the Bridge Control Register of
Device 1 (the SERRE bit of the PCI Command register of Device 1 must also be
a 1).
PRCOMP_AGP0 I
Compensation for AGP: This signal is used to calibrate the AGP buffers. It
needs to be pulled up to VCC_AGP through a 40 Ω resistor.
PRCOMP_AGP1
I/O
CMOS
Compensation for AGP: This signal is used to calibrate the AGP buffers. It
needs to be pulled up to VCC_AGP through a 40 Ω resistor.
PREF_AGP0
I
Analog
AGP Reference 0: Provides the VREF for AGP signals. The PREF_AGP0
signal is the switching point for the signaling on the AGP bus. The signals are
tied together on the MCH side.
PREF_AGP1
I
Analog
AGP Reference 1: Provides the VREF for AGP signals. The PREF_AGP1
signal is the switching point for the signaling on the AGP bus. The signals are
tied together on the MCH side.
PSWNG_AGP0
I
Analog
PSWNG_AGP0: This signal provides a reference voltage used by the AGP
RCOMP0 circuit. This signal is derived from 1.5 V by a resistor divider circuit.
The max level for this signal is 0.8 V
PSWNG_AGP1
I
Analog
PSWNG_AGP1: This signal provides a reference voltage used by the AGP
RCOMP1 circuit. This signal is derived from 1.5 V by a resistor divider circuit.
The max level for this signal is 0.8 V.
Table 2-8. AGP Command/ Control Signals (Sheet 2 of 2)
Signal Name Type Description