Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 175
Electrical Characteristics
6.3 I/O Interface Signal Groupings
The signal description includes the type of buffer used for the particular signal:
• AGTL+ Open Drain AGTL+ interface signal. The MCH integrates AGTL+ termination
resistors.
• CMOS 1.2 V CMOS buffers.
• SSTL-2 DDR Signaling Interface
• HI-2 Hub Interface buffer type
• AGP AGP Interface Buffer Type
NOTE: 1. x = A, B DDR channel
Table 6-3. Signal Groups System Bus Interface
Signal
Group
Signal Type Signals Notes
(a) AGTL+ I/O
AP [1:0]#, ADS#, BNR#, DBSY#, DEP [3:0]#, DRDY#, HA [35:3]#,
HADSTB [1:0] #, HD [63:0], HDSTBP [3:0]#, HDSTBN [3:0]#,
HIT#, HITM#, HREQ [4:0]#, BREQ0#, DINV [3;0]#, HXRCOMP,
HYRCOMP
(b) AGTL+ Output BPRI#, CPURST#, DEFER#, HTRDY#, RS [2:0]#, RSP#
(c) AGTL+ Input HLOCK#, XERR#, BINIT#
(d) Analog Input HDVREF [3:0], HAVREF [1:0], CCVREF, HXSWNG, HYSWNG
(e) CLK Inputs HCLKINN, HCLKINP
(f)
AGTL+
Termination
Voltage
VTT
Table 6-4. Signal Groups DDR Interface
Signal
Group
Signal Type Signals Notes
(g) SSTL-2 I/O DQ_x [63:0], CB_x [7:0], DQS_x [17:0], DRCOMP_x, ODTCOMP 1
(h) SSTL-2 Output
CMDCLK_x[6:0], CMDCLK_x[6:0]#, CS_x[5:0], CS_x[5:0]#,
MA_x[13:0], BA_x[1:0], RAS_x#, CAS_x#, WE_x#, CKE_x[3:0],
RCVENOUT_x#
1
(i) SSTL-2 Input DDRSTRAP 1
(j) Analog Input DVREF_x, DRCOMPVREF_x 1