Hub Datasheet

150 Intel
®
E7505 Chipset MCH Datasheet
System Address Map
4.1.3 I/O APIC Memory Space
The I/O APIC spaces are used to communicate with I/O APIC interrupt controllers that may be
populated on HI_A through HI_B. Since it is difficult to relocate an interrupt controller using plug-
and-play software, fixed address decode regions have been allocated for them. The address ranges
are:
• I/OAPIC0 (HI_A) 0_FEC0_0000h to 0_FEC7_FFFFh
• I/OAPIC1 (HI_B) 0_FEC8_0000h to 0_FEC8_0FFFh
Processor accesses to the IOAPIC0 region are always sent to HI_A. Processor accesses to the
IOAPIC1 region are always sent to HI_B and so on.
4.1.4 System Bus Interrupt Memory Space
The System bus interrupt space (0_FEE0_0000h to 0_FEEF_FFFFh) is the address used to deliver
interrupts to the System Bus. Any device on HI_A, HI_B may issue a DWord memory write to
0FEEx_xxxxh. The MCH will forward this memory write along with the data to the System Bus as
an Interrupt Message Transaction. The MCH terminates the system bus transaction by providing
the response and asserting TRDY#. This memory write cycle does not go to DRAM.
The processors may also use this region to send inter-processor interrupts (IPI) from one processor
to another.
4.1.5 High SMM Memory Space
The HIGHSMM space (0_FEDA_0000h to 0_FEDB_FFFFh) allows cacheable access to the
compatible SMM space by remapping valid SMM accesses between 0_FEDA_0000 and
0_FEDB_FFFFh to accesses between 0_000A_0000h and 0_000B_FFFFh. The accesses are
remapped when SMRAM space is enabled; an appropriate access is detected on the system bus,
and when ESMRAMC.H_SMRAME allows access to high SMRAM space. SMM memory
accesses from any HI port are specially terminated: reads are provided with the value from address
0 while writes are ignored entirely.
4.1.6 AGP Aperture Space (Device 0 and Device 1 BAR)
Processors and AGP devices communicate through a special buffer called the “graphics aperture.”
This aperture acts as a window into main DRAM memory and is defined by the APBASE and
APSIZE configuration registers of the MCH. Note that the AGP aperture must be above the top of
memory and must not intersect with any other address space.
• AGPAPP APBASE to APBASE + APSIZE
• AGPAPP1 APBASE1 to APBASE1 + APSIZE1
Note: Only one of the apertures (Device 0 or Device 1) will be used at any given time. This is determined
by which Device’s AGP Enable bit is on. However, both apertures will take space in the memory
map unless reclaimed.