Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 131
Register Description
3.8.16 MBASE2—Memory Base Address Register (D2:F0)
Address Offset: 20–21h
Default Value: FFF0h
Attribute: R/W, RO
Size: 16 bits
This register controls the processor-to-HI_B non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE2 ≤ address ≤ MEMORY_LIMIT2
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20
of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.
This register must be initialized by the configuration software. For the purpose of address decode,
address bits A19:0 are assumed to be 0. Thus, the bottom of the defined memory address range will
be aligned to a 1-MB boundary.
3.8.17 MLIMIT2—Memory Limit Address Register (D2:F0)
Address Offset: 22–23h
Default Value: 0000h
Attribute: R/W, RO
Size: 16 bits
This register controls the processor-to-HI_B non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20
of the 32-bit address. The bottom four bits of this register are read only and return zeroes when
read. This register must be initialized by the configuration software. For the purpose of address
decode, address bits A19:0 are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1-MB aligned memory block.
Bits
Default,
Access
Description
15:4
FFFh
R/W
Memory Address Base (MBASE). These bits corresponds to A31:20 of the lower limit
of the memory range that will be passed by the device 2 bridge to HI_B
3:0 Reserved
Bits
Default,
Access
Description
15:4
000h
R/W
Memory Address Limit (MILIMIT). These bits corresponds to A31:20 of the memory
address that corresponds to the upper limit of the range of memory accesses that will
be passed by the device 2 bridge to HI_B.
3:0 Reserved