Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 109
Register Description
3.7.18 MBASE1—Memory Base Address Register (D1:F0)
Address Offset: 20–21h
Default Value: FFF0h
Attribute: R/W, RO
Size: 16 bits
This register controls the processor-to-AGP non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20
of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.
This register must be initialized by the configuration software. For the purpose of address decode,
address bits A19:0 are assumed to be 0. Thus, the bottom of the defined memory address range will
be aligned to a 1-MB boundary.
Bits
Default,
Access
Description
15:4
FFFh
R/W
Memory Address Base (MBASE). This field corresponds to A31:20 of the lower limit of
the memory range that will be passed by the device 1 bridge to AGP.
3:0 Reserved