Hub Datasheet

106 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.14 SMLT1—Secondary Bus Master Latency Timer Register
(D1:F0)
Address Offset: 1Bh
Default Value: 00h
Attribute: R/W, RO
Size: 8 bits
This register controls the bus tenure of the MCH on AGP/PCI the same way device 0 MLT controls
the access to the PCI_A bus.
3.7.15 IOBASE1—I/O Base Address Register (D1:F0)
Address Offset: 1Ch
Default Value: F0h
Attribute: R/W, RO
Size: 8 bits
This register control the processor-to-AGP I/O access routing based on the following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A11:0 are
treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bits
Default,
Access
Description
7:3
00000b
R/W
Secondary MLT Counter Value (MLT). Programmable, default = 0 (SMLT disabled)
2:0 Reserved
Bits
Default,
Access
Description
7:4
Fh
R/W
I/O Address Base (IOBASE). These bits correspond to A15:12 of the I/O addresses
passed by bridge 1 to AGP.
3:0 Reserved