Datasheet

Datasheet 177
Host-Primary PCI Express* Bridge Registers (D1:F0)
6RW0b
Common Clock Configuration (CCC):
0 = Indicates that this component and the component at the opposite end of this
Link are operating with asynchronous reference clock.
1 = Indicates that this component and the component at the opposite end of this
Link are operating with a distributed common reference clock.
The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the
N_FTS value advertised during link training.
5RW/SC0b
Retrain Link (RL):
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from
L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read.
This bit is cleared automatically (no need to write a 0).
It is permitted to write 1b to this bit while simultaneously writing modified values
to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the
LTSSM is already in Recovery or Configuration, the modified values are not
required to affect the Link training that's already in progress.
4RW0b
Link Disable (LD):
0 = Normal operation.
1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via
Recovery) from L0, L0s, or L1 states. Link retraining happens automatically
on 0 to 1 transition, just like when coming out of reset.
Writes to this bit are immediately reflected in the value read from the bit,
regardless of actual Link state.
3RO0bRead Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte.
2 RO 0b Reserved
1:0 RW 00b
Active State PM (ASPM): Controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
Bit Access
Default
Value
Description