Specification Update

Intel
®
Xeon
®
Processor 7000 Series 15
Specification Update, March 2010
A37 X No Fix IA32_MCi_STATUS MSR may improperly indicate that additional MCA information
may have been captured
A38 X No Fix With trap flag (TF) asserted, FP instruction that triggers an unmasked FP exception
may take single step trap before retirement of instruction
A39 X No Fix Branch trace store (BTS) and precise event based sampling (PEBS) may update
memory outside the BTS/PEBS buffer
A40 X No Fix Memory ordering failure may occur with snoop filtering third party agents after
issuing and completing a bus write invalidate line (BWIL) or bus locked write (BLW)
transaction
A41 X No Fix Control register 2 (CR2) can be updated during a REP MOVS/STOS instruction
with fast strings enabled
A42 X No Fix REP STOS/MOVS instructions with RCX >= 2^32 may cause a system hang
A43 X No Fix An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute
to completion or may write to incorrect memory locations on processors supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
A44 X No Fix An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >=
2^32 may cause a system hang on processors supporting Intel
®
Extended Memory
64 Technology (Intel
®
EM64T)
A45 X No Fix Data access which spans both canonical and non-canonical address space may
hang system
A46 X No Fix Running in SMM and L1 data cache adaptive mode may cause unexpected system
behavior when SMRAM is mapped to cacheable memory
A47 X No Fix A 64-bit value of linear instruction pointer (LIP) may be reported incorrectly in the
branch trace store (BTS) memory record or in the precise event based sampling
(PEBS) memory record
A48 X No Fix PDE/PTE Loads and continuous locked updates to the same cache line may cause
a system livelock
A49 X No Fix At core-to-bus ratios of 16:1 and above defer reply transactions with non-zero
REQb Values; may cause a front side bus stall
A50 X No Fix CPUID reports thermal monitor 2 supported when running at ratios 18:1 and above
A51 X No Fix The processor may issue front side bus transactions up to 6 clocks after RESET#
is asserted
A52 X No Fix Front side bus machine checks may be reported as a result of on-going
transactions during warm reset
A53 X No Fix Entering single logical processor mode via power on configuration may not work
A54 X No Fix Machine check exception may be signaled in a system with multiple threads and
several lock transactions
A55 X No Fix The processor may issue multiple code fetches to the same cache line for systems
with slow memory
A56 X No Fix Writing the local vector table (LVT) when an interrupt is pending may cause an
unexpected interrupt
A57 X No Fix IRET under certain conditions may cause an unexpected alignment check
exception
A58 X Plan Fix Running with Virtual Machine Extensions (VMX) in L1 data cache adaptive mode
may cause unexpected system behavior
A59 X Plan Fix A mispredicted branch may issue a speculative load to an incorrect address during
VM exit on processors supporting Intel
®
Virtualization Technology
Table 2. Errata (Sheet 3 of 5)
Number A-0 Status Description