Specification Update

Errata
46 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF109 PCIe* Header of a Malformed TLP is Logged Incorrectly
Problem: If a PCIe port receives a malformed TLP (Transaction Layer Packet), an error is logged
in the UNCERRSTS register (Device 0; Function 0; Offset 14CH and Device 2-3;
Function 0-3; Offset 14CH). Due to this erratum, the header of the malformed TLP is
logged incorrectly in the HDRLOG register (Device 0; Function 0; Offset 164H and
Device 2-3; Function 0-3; Offset 164H).
Implication: The PCIe header of a malformed TLP is not logged correctly.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF110 PCIe* May Associate Lanes That Are Not Part of Initial Link Training to
L0 During Upconfiguration
Problem: The processor should not associate any lanes that were not part of the initial link
training in subsequent upconfiguration requests from an endpoint. Due to this erratum,
the processor may associate any Lane that has exited Electrical Idle, even if it is
beyond the width of the initial Link training.
Implication: Upconfiguration requests may result in a Link wider than the initially-trained Link.
Workaround: Endpoints must ensure that upconfiguration requests do not request a Link width wider
than that negotiated during initial Link training.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF111 Single PCIe* ACS Violation or UR Response May Result in Multiple
Correctable Errors Logged
Problem: An ACS (Access Control Services) error or UR (Unsupported Request) PCIe completion
status can trigger a LER (Live Error Recovery) if they are unmasked in the
LER_UNCERRMSK (Bus 0; Device 0/1/2/3; Function 0/0-1/0-3/0-3; Offset 28CH) and
LER_XPUNCERRMSK (Bus 0; Device 0/1/2/3; Function 0/0-1/0-3/0-3; Offset 290H)
CSRs, respectively. Due to this erratum, the Root Port Error Status
“multiple_correctable_error_received” bit (RPERRSTS[1], CPUBUSNO(0), Device 0:3,
Functions 0/0-1/0-3/0-3, Offset 0x178) may be set upon on a single ACS or UR error.
Implication: PCIe error handling software may not behave as expected after an ACS error or a UR
completion status. Intel has not observed this erratum with any commercially available
software or system.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF112 PCIe* Extended Tag Field May be Improperly Set
Problem: The Extended Tag field in the TLP Header will not be zero for TLPs issued by PCIe ports
1a, 1b, 2c, 2d, 3c, and 3d even when the Extended Tag Field Enable bit in the Device
Control Register (Offset 08H, bit 8) is 0.
Implication: This erratum does not affect ports 0, 2a, 2b, 3a and 3b. This erratum will not result in
any functional issues when using device that properly track and return the full 8 bit
Extended Tag value with the affected ports. However, if the Extended Tag field is not
returned by a device connected to an affected port then this erratum may result in
unexpected completions and completion timeouts.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF113 Power Meter May Under-Estimate Package Power
Problem: Power Meter provides a real-time power consumption estimate for the processor.
Depending on operating conditions and variations in certain component-specific
characteristics, the reported power may be below the actual power consumption.