Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 31
Specification Update January 2015
CF47 Concurrently Changing the Memory Type and Page Size May Lead to a
System Hang
Problem: Under a complex set of microarchitectural conditions, the system may hang if software
changes the memory type and page size used to translate a linear address while a TLB
(Translation Lookaside Buffer) holds a valid translation for that linear address.
Implication: Due to this erratum, the system may hang. Intel has not observed this erratum with
any commercially available software.
Workaround: None identified. Please refer to Software Developer’s Manual, volume 3, section
“Recommended Invalidation” for the proper procedure for concurrently changing page
attributes and page size.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF48 MCI_ADDR May be Incorrect For Cache Parity Errors
Problem: In cases when a WBINVD instruction evicts a line containing an address or data parity
error (IA32_MC1_STATUS.MCACOD of 0x174 and IA32_MC1_STATUS.MSCOD of 0x10),
the address of this error should be logged in the IA32_MC1_ADDR register. Due to this
erratum, the logged address may be incorrect, even though IA32_MC1_Status.ADDRV
(bit 63) is set.
Implication: The address reported in IA32_MC1_ADDR may not be correct for cases of a parity error
found during WBINVD execution.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF49 Instruction Fetches Page-Table Walks May be Made Speculatively to
Uncacheable Memory
Problem: Page-table walks on behalf of instruction fetches may be made speculatively to
uncacheable (UC) memory.
Implication: If any paging structures are located at addresses in uncacheable memory that are used
for memory-mapped I/O, such I/O operations may be invoked as a result of speculative
execution that would never actually occur in the executed code path. Intel has not
observed this erratum with any commercially available software.
Workaround: Software should avoid locating paging structures at addresses in uncacheable memory
that are used for memory-mapped I/O.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF50 REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem: Under certain conditions as described in the Software Developers Manual section “Out-
of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.