Specification Update

Errata
30 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
Implication: The INVVPID instruction may fail to invalidate translations for linear addresses that set
bits in the range 63:32. Because this erratum applies only to executions outside 64-bit
mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to
invalidate translations for a 64-bit guest. Intel has not observed this erratum with any
commercially available software.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF44 REP MOVSB May Incorrectly Update ECX, ESI, and EDI
Problem: Under certain conditions, if the execution of a REP MOVSB instruction is interrupted,
the values of ECX, ESI and EDI may contain values that represent a later point in the
execution of the instruction than the actual interruption point.
Implication: Due to this erratum ECX, ESI, and EDI may be incorrectly advanced, resulting in
unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the Table 1, “Summary Table of Changes”.
CF45 Performance-Counter Overflow Indication May Cause Undesired
Behavior
Problem: Under certain conditions (listed below) when a performance counter overflows, its
overflow indication may remain set indefinitely. This erratum affects the general-
purpose performance counters IA32_PMC{0-7} and the fixed-function performance
counters IA32_FIXED_CTR{0-2}. The erratum may occur if any of the following
conditions are applied concurrent to when an actual counter overflow condition
is reached:
1. Software disables the counter either globally through the
IA32_PERF_GLOBAL_CTRL MSR (38FH), or locally through the
IA32_PERFEVTSEL{0-7} MSRs (186H-18DH), or the IA32_FIXED_CTR_CTRL MSR
(38DH).
2. Software sets the IA32_DEBUGCTL MSR (1D9H) FREEZE_PERFMON_ON_PMI bit
[12].
3. The processor attempts to disable the counters by updating the state of the
IA32_PERF_GLOBAL_CTRL MSR (38FH) as part of transitions such as VM exit, VM
entry, SMI, RSM, or processor C-state.
Implication: Due to this erratum, the corresponding overflow status bit in
IA32_PERF_GLOBAL_STATUS MSR (38DH) for an affected counter may not get cleared
when expected. If a corresponding counter is configured to issue a PMI (performance
monitor interrupt), multiple PMIs may be signaled from the same overflow condition.
Likewise, if a corresponding counter is configured in PEBS mode (applies to only the
general purpose counters), multiple PEBS events may be signaled.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF46 VEX.L is not Ignored with VCVT*2SI Instructions
Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and
VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and
will cause a #UD.
Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI,
VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions.
Workaround: Software should ensure that the VEX.L bit is set to 0 for all scalar instructions.
Status: For the affected steppings, see the “Summary Table of Changes”.