Specification Update

Errata
24 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF21 Functionally Benign PCIe* Electrical Specification Violation
Compendium.
Problem: Violations of PCIe* electrical specifications listed in the table below have been
observed.
Implication: Intel has not observed failures from the violations listed in this erratum on any
commercially available platforms and/or using commercially available PCIe* devices.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF22 Patrol Scrubbing During Memory Mirroring May Improperly Signal
Uncorrectable Machine Checks.
Problem: With memory mirroring enabled, Patrol Scrub detection of an uncorrectable error on
one channel of the mirror should be downgraded to a correctable error when valid data
is present on the other channel of the mirror. Due to this erratum, patrol Scrub
detection of an uncorrectable error always signals an uncorrectable Machine Check.
Implication: This erratum may cause reduced availability of systems with mirrored memory.
Workaround: It is possible for BIOS to contain processor configuration data and code changes as a
workaround for this erratum. Refer to Intel® Xeon® Processor E7 v2 Product Family-
based Platform CPU/Intel
®
QPI/Memory Reference Code version 1.0 or later and
release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF23 A Modification To The Multiple Message Enable Field Does Not Affect
The AER Interrupt Message Number Field.
Problem: The (Advanced Error Interrupt) Message Number field (RPERRSTS Devices 0-3;
Functions 0-3; Offset 178H; bits[31:27]) should be updated when the number of
messages allocated to the root port is changed by writing the Multiple Message Enable
field (MSIMSGCTL Device 3; Function 0; Offset 62H; bits[6:4]). However, writing the
Multiple Message Enable in the root port does not update the Advanced Error Interrupt
Message Number field.
Implication: Due to this erratum, software can allocate only one MSI (Message Signaled Interrupt)
to the root port.
Workaround: None identified
Status: For the affected steppings, see the “Summary Table of Changes”.
Specification Violation Description
Deemphasis ratio limit: -3.5±0.5 dB Ave: -3.8 dB, Min: -4.09 dB
At 5 GT/s operation, the receiver must tolerate AC
common mode voltage of 300 mV (peak-to-peak) and
must tolerate 78.1 ps jitter.
Simultaneous worst case AC common mode voltage
and worst case jitter during 5 GT/s operation may
result in intermittent failures leading to subsequent
recovery events.
TTX-UPW-TJ (uncorrelated total pulse width jitter)
maximum of 24 ps.
Samples have measured as high as 25 ps.
The Transmitter PLL bandwidth and peaking for PCIe*
at 5 GT/s is either 8 to 16 MHz with 3 dB of peaking or
5 to 16 MHz with 1 dB of peaking.
Samples have measured 7.8-16 MHz with 1.3 dB of
peaking.
During the LTSSM Receiver Detect State, common-
mode resistance to ground is 40 to 60 ohms.
Samples have measured up to 100 ohms.
8 GT/s Receiver Stressed Eye Samples marginally pass or fail the 10-12 BER target
under stressed eye conditions.
8 GT/s PLL Bandwidth: 2 to 4 MHz with 2 dB peaking. Samples have a measured bandwidth of up to 4.1 MHz