Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 21
Specification Update January 2015
CF8 PCIe* TPH Attributes May Result in Unpredictable System Behavior.
Problem: TPH (Transactions Processing Hints) are optional aids to optimize internal processing of
PCIe* transactions. Due to this erratum, certain transactions with TPH attributes may
be misdirected, resulting in unpredictable system behavior.
Implication: Use of the TPH feature may affect system stability.
Workaround: A BIOS workaround has been identified. Refer to Intel Xeon Processor E7 v2 Family-
based Platform CPU/Intel
®
QPI/Memory Reference Code version 1.0.006 or later and
release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF9 PCIe* Rx Common Mode Return Loss is Not Meeting the Specification.
Problem: The PCIe* specification requires that the Rx Common Mode Return Loss in the range of
0.05 to 2.5 GHz must be limited to -6 dB. The processor’s PCIe* Rx do not meet this
requirement. The PCIe* Rx Common Mode Return at 500 MHz has been found to be
between -3.5 and -4 dB on a limited number of samples.
Implication: Intel has not observed any functional failures due to this erratum with any
commercially available PCIe* devices.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF10 Intel
®
QuickPath Interconnect (Intel
®
QPI) Tx AC Common Mode Fails
Specification.
Problem: The Intel
®
QuickPath Interconnect (Intel
®
QPI) specification requires Tx AC Common
Mode (ACCM) to be between -50 mV and 50 mV at 8.0 GT/s. Testing across process,
voltage, and temperature showed that the ACCM exceeded the upper end of the
specification on several lanes.
Implication: Those performing an electrical characterization of the Intel
®
QPI interface may notice a
violation of the upper end of the ACCM specification by no more than 5 mV.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF11 PCIe* Rx DC Common Mode Impedance is Not Meeting the
Specification.
Problem: When the PCIe* Rx termination is not powered, the DC Common Mode impedance has
the following requirement: ≥10 kohm over 0 to 200 mV range with respect to ground
and ≥20 kohm for voltages ≥200 mV with respect to ground. The processor’s PCIe* Rx
do not meet this requirement at 85°C or greater. In a limited number of samples Intel
has measured an impedance as low as 9.85 kohm at 50 mV.
Implication: Intel has not observed any functional impact due to this violation with any
commercially available system.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF12 QPILS Reports the VNA/VN0 Credits Available for the Processor Rx
Rather Than Tx.
Problem: The QPILS register (Bus 1; Devices 8,9, 24; Function 0; Offset 0x48), according to the
Intel
®
QuickPath Interconnect Specification at revision 1.1 and later, should report the
VNA/VN0 credits available for the processor Tx (Transmit port). Due to this erratum,
the QPILS register reports the VNA/VN0 credits available for the processor Rx (Receive
port).
Implication: This is a violation of the specification but no functional failures have been observed due
to this erratum.