Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 19
Specification Update January 2015
Errata
CF1 Core Frequencies at or Below the DRAM DDR Frequency May Result in
Unpredictable System Behavior.
Problem: The Enhanced Intel SpeedStep
®
Technology can dynamically adjust the core operating
frequency to as low as 1200 MHz. Due to this erratum, under complex conditions and
when the cores are operating at or below the DRAM DDR frequency, unpredictable
system behavior may result.
Implication: Systems using Enhanced Intel SpeedStep Technology with DDR3-1333 or DDR3-1600
memory devices are subject to unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF2 DWORD Aligned XOR DMA Sources May Prevent Further DMA XOR
Progress.
Problem: XOR DMA channels may stop further progress in the presence of Locks/PHOLDs if the
source pointed to by a DMA XOR descriptor is not cacheline aligned.
Implication: Non-cacheline aligned DMA XOR sources may hang both channels 0 and 1. A reset is
required in order to recover from the hang. Legacy DMA descriptors on any channel
have no source alignment restrictions.
Workaround: Software must either:
• Ensure XOR DMA descriptors only point to cacheline aligned sources (best
performance) OR
• A legacy DMA copy must be used prior to non-cacheline aligned DMA operations to
guarantee that the source misalignment is on DWORD15 of the cacheline. The
required source that must be misaligned to DWORD15, depends on the following
desired subsequent DMA XOR operations:
— DMA XOR Validate (RAID5/ P-Only): The P-source must be misaligned to
DWORD15 (last DWORD).
— DMA XOR Validate (RAID6/P+Q): The Q-source must be misaligned to
DWORD15 (last DWORD).
— DMA XOR Generate or Update: The last source (which will be different based on
numblk) must be misaligned to DWORD15 (last DWORD).
Status: For the affected steppings, see the “Summary Table of Changes”.
CF3 Rank Sparing May Cause an Extended System Stall.
Problem: The Integrated Memory Controller sequencing during a rank sparing copy operation
blocks all writes to the memory region associated with the rank being taken out of
service. Due to this erratum, this block can result in a system stall that persists until
the sparing copy operation completes.
Implication: The system can stall at unpredictable times which may be observed as one time
instance of system unavailability.
Workaround: A BIOS workaround has been identified. Refer to Intel Xeon Processor E7 v2 Product
Family-based Platform CPU/Intel QPI/Memory Reference Code version 1.0.006 or later
and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.