Hub Datasheet

78 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.36 REMAPLIMIT—Remap Limit Address Register (D0:F0)
Address Offset: C8–C9h
Default Value: 0000h
Attribute: RO, R/W
Size: 16 bits
3.5.37 SKPD—Scratch Pad Data Register (D0:F0)
Address Offset: DE–DFh
Default Value: 0000h
Attribute: R/W
Size: 16 bits
3.5.38 DVNP—Device Not Present Register (D0:F0)
Address Offset: E0–E1h
Default Value: 1D1Fh
Attribute: RO, R/W
Size: 32 bits
Bits
Default,
Access
Description
15:10 Reserved
9:0
00h
R/W
Remap Limit Address 35:26. The value in this register defines the upper boundary of
the Remap window. The Remap window is inclusive of this address. In the decoder
A25:0 of the Remap Limit Address are assumed to be Fhs. Thus, the top of the defined
range will be one less than a 64-MB boundary.
When the value in this register is less than the value programmed into the Remap Base
register, the Remap window is disabled. This field defaults to 0000h.
Bits
Default,
Access
Description
15:0
0000h
R/W
Scratch pad (SCRTCH). These bits are R/W storage bits that have no effect on the
MCH functionality.
Bits
Default,
Access
Description
15:3 Reserved
2
1b
R/W
Device 2, Function 1 Hide.
0 = Present
1 = Not present. Accesses from the processor are disabled when this bit is set.
1 Reserved
0
1b
R/W
Device 0, Function 1 Hide.
0 = Present
1 = Not present. Accesses from the processor are disabled when this bit is set.