Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 75
Register Description
3.5.31 ATTBASE—Aperture Translation Table Register (D0:F0)
Address Offset: B8–BBh
Default Value: 0000 0000h
Attribute: R/W
Size: 32 bits
This register provides the starting address of the Graphics Aperture Translation Table (GART)
Base located in the main memory. This value is used by the MCH’s Graphics Aperture address
translation logic (including the GTLB logic) to obtain the appropriate address translation entry
required during the translation of the aperture address into a corresponding physical main memory
address. The ATTBASE register may be dynamically changed. Set by drivers.
3.5.32 AMTT—AGP MTT Control Register (D0:F0)
Address Offset: BCh
Default Value: 00h
Attribute: RO, R/W
Size: 8 bits
AMTT is an 8-bit register that controls the amount of time that the MCH’s arbiter allows AGP/PCI
master to perform multiple back-to-back transactions. The MCH’s AMTT mechanism is used to
optimize the performance of the AGP master (using PCI semantics) that performs multiple back-
to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst
transfers). The AMTT mechanism applies to the processor-AGP/PCI transactions as well and it
assures the processor of a fair share of the AGP/PCI interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after which
the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables
this function. The AMTT value can be programmed with 8-clock granularity. For example, if the
AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP
(66 MHz) clocks. Set by BIOS.
Bits
Default,
Access
Description
31:12
0...0b
R/W
Aperture Translation Table Base (TTABLE). This field contains a pointer to the base of
the translation table used to map memory space addresses in the aperture range to
addresses in main memory. Note that it should be modified only when the GTLB has
been disabled.
11:0 Reserved
Bits
Default,
Access
Description
7:3
00000b
R/W
Multi-Transaction Timer Count Value (MTTC). The number programmed into these bits
represents the time slice (measured in eight 66 MHz clock granularity) allotted to the
current agent (either AGP/PCI master or Host bridge) after which the AGP arbiter will
grant the bus to another agent.
2:0 Reserved