Hub Datasheet

74 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.30 APSIZE—Aperture Size Register (D0:F0)
Address Offset: B4h
Default Value: 00h
Attribute: RO, R/W
Size: 8 bits
This register determines the effective size of the Graphics Aperture used for a particular MCH
configuration. This register can be updated by the MCH-specific BIOS configuration sequence
before the PCI standard bus enumeration sequence takes place. If the register is not updated, the
default value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will
correspond to a 256-MB aperture is not practical for most applications; therefore, these bits must
be programmed to a smaller practical value that will force adequate address range to be requested
via APBASE register from the PCI configuration software. Set by BIOS.
Bits
Default,
Access
Description
7:6 Reserved
5:0
00h
R/W
Graphics Aperture Size (APSIZE). Each bit in APSIZE5:0 operates on similarly
ordered bits in APBASE27:22 of the Aperture Base configuration register. When a
particular bit of this field is 0, it forces the similarly ordered bit in APBASE27:22 to
behave as “hardwired” to 0. When a particular bit of this field is set to 1, it allows
corresponding bit of the APBASE27:22 to be read/write accessible. The default value
(APSIZE5:0=000000b) forces the default APBASE27:22 to read as 000000b
(i.e., all bits respond as hardwired to 0). This provides the maximum aperture size of
256 MB. As another example, programming APSIZE5:0 to 111000b hardwires
APBASE24:22 to 000b and enables APBASE27:25 to be read/write programmable.
000000 = 256-MB Aperture Size
100000 = 128-MB Aperture Size
110000 = 64-MB Aperture Size
111000 = 32-MB Aperture Size
111100 = 16-MB Aperture Size
111110 = 8-MB Aperture Size
111111 = 4-MB Aperture Size