Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 153
System Address Map
4.3.3 High SMM Memory Space
The HIGHSMM space (0_FEDA_0000h to 0_FEDB_FFFFh) allows cacheable access to the
compatible SMM space by remapping valid SMM accesses between 0_FEDA_0000h and
0_FEDB_FFFFh to accesses between 0_000A_0000h and 0_000B_FFFFh. The accesses are
remapped when SMRAM space is enabled; an appropriate access is detected on the system bus,
and when ESMRAMC.H_SMRAME allows access to high SMRAM space. SMM memory
accesses from any hub interface are specially terminated: reads are provided with the value from
address 0 while writes are ignored entirely.
4.3.4 SMM Space Restrictions
When any of the following conditions are violated, the results of SMM accesses are unpredictable
and may cause undesirable system behavior:
1. The Compatible SMM space must not be setup as cacheable.
2. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
3. When TSEG SMM space is enabled, the TSEG space must not be reported to the operating
system as available DRAM. This is a BIOS responsibility.
4.3.5 SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the processor to access SMM space.
DRAM SMM space is defined as the range of physical DRAM memory locations containing the
SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible,
High, and TSEG. The Compatible and TSEG SMM space is not remapped and, therefore, the
addressed and DRAM SMM space is the same address range. Since the High SMM space is
remapped, the addressed and DRAM SMM space is a different address range. Note that the High
DRAM space is the same as the Compatible Transaction Address space. Table 4-1 describes three
unique address ranges:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Table 4-1. SMM Address Range
NOTES:
1. High SMM: This is different than in previous chipsets. In previous chipsets the High segment was the 384 KB
region from A_0000h to F_FFFFh. However, C_0000h to F_FFFFh was not practically useful so it is deleted
in the MCH.
2. TSEG SMM: This is different than in previous chipsets. In previous chipsets the TSEG address space was
offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just under the TOLM. In the
MCH the TSEG region is not offset by 256 MB and it is not remapped.
SMM Space Enabled Transaction Address Space DRAM Space
Compatible A0000h to BFFFFh A0000h to BFFFFh
High 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh
TSEG (TOLM–TSEG_SZ) to TOLM (TOLM–TSEG_SZ) to TOLM