Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 13
Intel
®
E7505 Chipset MCH Features
■ Processor/Host Bus Support
— Symmetric Multiprocessing Protocol (SMP) for up
to two processors
— 533 MHz or 400 MHz (2x address, 4x data)
— System Bus Dynamic Bus Inversion (DBI)
— 36-bit host bus addressing
— 12-deep in-order queue
— 2-deep defer queue (only one per HI)
— AGTL+ bus driver technology with on-die
termination resistors
— Parity protection on host bus Data, Address/
Request, and Response signals
■ Memory System
— Dual Channel (144-bits wide) DDR memory
interface
— DDR200 (PC1600) and DDR266 (PC2100)
operation
— Synchronous operation with processor system bus
(same clock frequency required on both)
— 128-Mb, 256-Mb, 512-Mb, 1-Gb DRAM densities
— Maximum system memory is 16 GB
— x64 or x72 DIMMs using x4, x8, or x16 DRAM
devices (x4 registered only, x16 unbuffered only)
Note: Double-sided x16 is not supported
— Based on three DIMMs - 24 simultaneous open
pages (4 per row)
— Non-ECC mode (64-bit DIMMs)
— Registered or unbuffered DIMMs
— DIMMs must be populated in identical pairs for
dual channel operation
—Intel
®
x4 Single Device Data Correction
(x4 SDDC) technology ECC supported
- Corrects any number of errors contained in 4-bit
naturally aligned nibbles
- Detects all errors contained entirely within two
4-bit naturally aligned nibbles
— Opportunistic DRAM refresh
■ Accelerated Graphics Port (AGP)
— AGP Specification 3.0
— Single AGP device
— AGP interface asynchronously coupled to core
— AGP 8x / 4x (0.8 V swing) and 4x, 2x, 1x (1.5 V
swing)
— No 3.3 V support
— 32 deep AGP request queue
— 32-bit upstream address support for inbound AGP
and PCI cycles
— 32-bit downstream address support for outbound
PCI and Fast Write cycles
— AGP address translation mechanism with two
integrated fully associative 20 entry TLBs
— AGP register set in both Device 0 and Device 1
■ Hub Interface_A to Intel
®
ICH4
— Connection to ICH4 via HI1.5 (HI1.0 protocol and
data rate, HI2.0 electrical characteristics)
— 8-bit interface
— 266 MT/s point-to-point HI1.5 interface to ICH4
with parity
— 66 MHz base clock
— All HI IB accesses are snooped
— Isochronous support
— Parallel termination mode only
— Asynchronously coupled to core
— 64-bit addressing on IB transactions (maximum
16-GB memory decode space
1
)
— 32-bit OB addressing
— Supports the following traffic types to ICH4: HI-
to-AGP memory writes, HI-to-DRAM, Processor-
to-HI, Messaging
— MSI Interrupt messages
— Power Management state change
— SMI, SCI and SERR error indication
■ Hub Interface_B
— HI2.0 protocols and electrical characteristics
— Independent 1 GB/s point-to-point 16-bit
connection
— ECC protection
— 66 MHz base clock running 8x (1 GB/s) data
transfers
— Snooped and non-snooped IB accesses
— Asynchronously coupled to core
— Parallel termination mode only
— 64-bit IB addressing
— 32-bit OB addressing for PCI-X
— Supports the following traffic types to ICH4: HI_B
to AGP/PCI_B memory writes, HI_B to DRAM
(memory reads and writes), CPU to HI_B
(memory reads or writes, I/O reads or writes),
MSIs between HI_A, Messaging
— MSI interrupt messages
— EOI Message
■ PCI Support
— 33 MHz PCI on ICH4
— 33 MHz and 66 MHz PCI on P64H2
— 66 MHz, 100 MHz, or 133 MHz for PCI-X on
P64H2
■ Power Management Support
— SMRAM space remapping to A0000h (128 KB)
— Extended SMRAM space above 256 MB
— SMRAM accesses from TSEG, AGP or HIs are not
allowed
— PC’99 Suspend to RAM (STR)
— ACPI Rev 2.0 compliant power management
— NT Hardware Design Guide v1.0 compliant
— APM Rev 1.2 compliant power management
— C0, C1, S0, S1 (DT), and S3
■ Package
— 1005 Ballout