Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 107

3.7.16 IOLIMIT1—I/O Limit Address Register (D1:F0)

Address Offset: 1Dh

Default Value: 00h

Attribute: R/W, RO

Size: 8 bits

This register controls the processor-to-AGP I/O access routing based on the following formula:

IO_BASE ≤ address ≤ IO_LIMIT1

Only the upper 4 bits are programmable. For the purpose of address decode, address bits A11:0 are

assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB

aligned address block.

Bits

Default,

Access

Description

7:4

R/W

I/O Address Limit (IOLIMIT). This field corresponds to A15:12 of the I/O address limit

of device 1. Devices between this upper limit and IOBASE1 will be passed to AGP.

3:0 Reserved