Datasheet

DRAM Controller Registers (D0:F0)
82 Datasheet
5.1.21 PAM4—Programmable Attribute Map 4
B/D/F/Type: 0/0/0/PCI
Address Offset: 94h
Default Value: 00h
Access: RO, RW/L
Size: 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D8000h – 0DFFFFh.
Bit Access
Default
Value
Description
7:6 RO 00b Reserved
5:4 RW/L 00b
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from 0DC000h
to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
3:2 RO 00b Reserved
1:0 RW/L 00b
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from 0D8000h
to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.