Datasheet

Datasheet 69
DRAM Controller Registers (D0:F0)
5.1.4 PCISTS—PCI Status
B/D/F/Type: 0/0/0/PCI
Address Offset: 6–7h
Default Value: 0090h
Access: RO, RWC
Size: 16 bits
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit Access
Default
Value
Description
15 RWC 0b
Detected Parity Error (DPE): This bit is set when this Device receives a
Poisoned TLP.
14 RWC 0b
Signaled System Error (SSE): This bit is set to 1 when the MCH Device 0
generates an SERR message over DMI for any enabled Device 0 error condition.
Device 0 error conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK
registers. Device 0 error flags are read/reset from the PCISTS, ERRSTS, or
DMIUEST registers. Software clears this bit by writing a 1 to it.
13 RWC 0b
Received Master Abort Status (RMAS): This bit is set when the MCH
generates a DMI request that receives an Unsupported Request completion
packet. Software clears this bit by writing a 1 to it.
12 RWC 0b
Received Target Abort Status (RTAS): This bit is set when the MCH
generates a DMI request that receives a Completer Abort completion packet.
Software clears this bit by writing a 1 to it.
11 RO 0b
Signaled Target Abort Status (STAS): The MCH will not generate a Target
Abort DMI completion packet or Special Cycle. This bit is not implemented in the
MCH and is hardwired to a 0. Writes to this bit position have no effect.
10:9 RO 00b
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit
positions have no affect. Device 0 does not physically connect to PCI_A. These
bits are set to "00" (fast decode) so that optimum DEVSEL timing for PCI_A is
not limited by the MCH.
8RWC0b
Master Data Parity Error Detected (DPD): This bit is set when DMI received
a Poisoned completion from ICH.
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
7RO1b
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit
positions have no effect. Device 0 does not physically connect to PCI_A. This bit
is set to 1 (indicating fast back-to-back capability) so that the optimum setting
for PCI_A is not limited by the MCH.
6 RO 0b Reserved
5RO0b66 MHz Capable: Does not apply to PCI Express. Hardwired to 0.
4RO1b
Capability List (CLIST): This bit is hardwired to 1 to indicate to the
configuration software that this device/function implements a list of new
capabilities. A list of new capabilities is accessed via register CAPPTR at
configuration address offset 34h. Register CAPPTR contains an offset pointing to
the start address within configuration space of this device where the Capability
Identification register resides.
3:0 RO 0000b Reserved