Datasheet

Datasheet 195
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.3 STS—Device Status
B/D/F/Type: 0/3/0/PCI
Address Offset: 6–7h
Default Value: 0010h
Access: RO
Size: 16 bits
7.1.4 RID—Revision ID
B/D/F/Type: 0/3/0/PCI
Address Offset: 8h
Default Value: see table below
Access: RO
Size: 8 bits
7.1.5 CC—Class Code
B/D/F/Type: 0/3/0/PCI
Address Offset: 9–Bh
Default Value: 0C8001h
Access: RO
Size: 24 bits
Bit Access
Default
Value
Description
15:5 RO 0h Reserved
4RO1b
Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to
1.
3RO0b
Interrupt Status (IS): Indicates the interrupt status of the device
1 = Asserted
2:0 RO 000b Reserved
Bit Access
Default
Value
Description
7:0 RO
See
Description
Revision ID (RID): This field indicates stepping of the HECI host controller.
Refer to the Intel
®
3200 and 3210 Chipset Specification Update for the value
of this register.
Bit Access
Default
Value
Description
23:16 RO 0ch
Base Class Code (BCC): Indicates the base class code of the HECI host
controller device.
15:8 RO 80h
Sub Class Code (SCC): Indicates the sub class code of the HECI host controller
device.
7:0 RO 01h
Programming Interface (PI): Indicates the programming interface of the
HECI host controller device.