Datasheet

14 Datasheet
Intel
®
3200 and 3210 Chipset
MCH Features
§
• Processor/Host Interface (FSB)
— Dual-Core Intel
®
Xeon
®
Processor 3000 Series
— Quad-Core Intel
®
Xeon
®
Processor 3200 Series
— 800/1067/1333 MT/s (200/266/333 MHz) FSB
— Hyper-Threading Technology (HT Technology)
— FSB Dynamic Bus Inversion (DBI)
— 36-bit host bus addressing
— 12-deep In-Order Queue
—1-deep Defer Queue
— GTL+ bus driver with integrated GTL termination resistors
— Supports cache Line Size of 64 bytes
• System Memory Interface
— One or two channels (each channel consisting of 64 data lines)
— Single or Dual Channel memory organization
— DDR2-800/667 frequencies
— Unbuffered, ECC and non-ECC DDR2 DIMMs
— Supports 1-Gb, 512-Mb DDR2
— 8 GB maximum memory
• Direct Media Interface (DMI)
— Chip-to-chip connection interface to Intel ICH9
— 2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction)
— 100 MHz reference clock (shared with PCI Express graphics
attach)
— 32-bit downstream addressing
— Messaging and Error Handling
• PCI Express* Interface
— 3210 MCH supports one x16 PCI Express port or two
x8 PCI Express ports
— 3200 MCH supports one x8 PCI Express port
— Compatible with the PCI Express Base Specification,
Revision 1.1
— Raw bit rate on data pins of 2.5 Gb/s resulting in a
real bandwidth per pair of 250 MB/s
• Thermal Sensor
— Catastrophic Trip Point support
— Hot Trip Point support for SMI generation
• Power Management
— ACPI Revision 2.0 compatible power management
— Supports processor states: C0, C1, C2
— Supports System states: S0, S1, and S5
— Supports processor Thermal Management 2
•Package
—FC-BGA
— 40 mm × 40 mm package size
—
1300 balls, located in a non-grid pattern