Specification Update

Intel
®
Xeon
®
Processor 7000 Series 25
Specification Update, March 2010
A21. xAPIC may not report some illegal vector error
Problem: The local xAPIC has an Error Status Register, which records all errors it detects. Bit 6 of
this register, the Receive Illegal Vector bit, is set when the local xAPIC detects an illegal
vector in a message that it receives. When an illegal vector error is received on the
same internal clock that the error status register is being written due to a previous
error, bit 6 does not get set and illegal vector errors are not flagged.
Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately
the same time as other xAPIC errors. The other xAPIC errors will continue to be
reported.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A22. Incorrect duty cycle is chosen when on-demand clock modulation is
enabled in a processor supporting Hyper-Threading Technology
Problem: When a processor supporting Hyper-Threading Technology enables On-Demand Clock
Modulation on both logical processors, the processor is expected to select the lowest
duty cycle of the two potentially different values. When one logical processor enters the
AUTOHALT state, the duty cycle implemented should be unaffected by the halted logical
processor. Due to this erratum, the duty cycle is incorrectly chosen to be the higher
duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock
Modulation is enabled on both logical processors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A23. Memory aliasing of pages as uncacheable memory type and write back
(WB) may hang the system
Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC)
and WB, under certain bus and memory timing conditions, the system may loop in a
continual sequence of UC fetch, implicit writeback, and Request For Ownership (RFO)
retries
Implication: This erratum has not been observed in any commercially available operating system or
application. The aliasing of memory regions, a condition necessary for this erratum to
occur, is documented as being unsupported in the IA-32 Intel
®
Architecture Software
Developer's Manual, Volume 3, section 10.12.4, Programming the PAT. However, if this
erratum occurs the system may hang
Workaround: The pages should not be mapped as either UC or WC and WB at the same time.
Status: For the steppings affected, see the Summary Table of Changes.
A24. Interactions between the instruction translation lookaside buffer
(ITLB) and the instruction streaming buffer may cause unpredictable
software behavior
Problem: Complex interactions within the instruction fetch/decode unit may make it possible for
the processor to execute instructions from an internal streaming buffer containing stale
or incorrect information.
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in
unpredictable software behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.